With the increasingly rapid change in integrated circuit fabrication processes and market conditions, the relationship between the yield and performance ramp and profitability is also undergoing rapid change. Typical yield vs. time and price vs. time graphs are shown in FIG. 1. Typical yield starts at an initial value Yinitial, and can eventually achieve a final value Yfinal when the process matures and production maximizes. Between the initial and final values is the yield ramp region 100, where yield is increasing at a yield ramp rate. This period also typically shows a lowering of the price at a price slope rate. Traditionally, yield improvement efforts focused mainly on reduction in defects, which would have a large impact on final yield. However, with the current situation of increasing complexity of processes coupled with shorter product lifetimes of integrated circuit products, there is generally minimal production at final yield, therefore final yield is a smaller factor in IC profitability. Improvements in initial yield (highly dependent on design) and yield ramp rate are far more important.
To this end, a critical factor in improving yield ramp rate is the gathering and statistical analysis of large amounts of experimental yield-relevant data within a short time span.
In recent years, a primary source of yield-relevant data is obtained via specially designed Test Chips, also called Characterization Vehicles (CV's). The CV's contain features which match one or more attributes of the proposed product layout, and are designed to support yield models which can be used for accurate yield prediction. These CV's, fabricated using a mask set and implementing all or a portion of the process used for the IC in question, comprise test structures which can be used to perform experiments that provide yield-relevant data. Examples include: snakes and combs for continuity/bridging, open via tests. Basic test structures are described in Buehler, M. G., Microelectronic Test Chips for VLSI Electronis, VLSI Electronics Microstructure Science, pp 529-576, Vol. 9, Chapter 9, Academic Press, 1983.
Due to the increasing density and complexity of IC structures and processes, including multiple layers of conducting interconnections, insulating layers, and connecting vias, as well as active devices, poly, and contacts, more and more test structures must be designed, manufactured, tested, and analyzed to enable a high quality Yield Impact Evaluation. More than 1,000 experiments may be required simply to characterize the Front End Of Line (FEOL), including Active Area (AA), Poly, and Contact. The FEOL CV's require more area for leakage and SRAM evaluation. Additional experiments are required to characterize up to 10 Back End Of Line (BEOL) metal and via layers.
In the current short time frames necessary for gathering information to enhance yield, fast feedback loops to accelerate yield learning, as well as fast test time, are critical. Data must be quickly provided in order to decide on process and layout changes to improve product yield. This requires the use of Short Flow's (SF's) whenever possible.
Short Flows are described in U.S. Pat. No. 6,834,375 by Stine et al, issued Dec. 21, 2004. A Short Flow is defined as encompassing only a specific subset of the total number of process steps in the integrated circuit fabrication cycle. Many Short Flow CV's in the art (an example of which is described in Hess, C., Stashower, D., Stine, B. E., Weiland, L. H., Verma, G., Miyamoto, K., Inoue, K., Fast Extraction of Defect Size Distribution Using a Single Layer Short Flow NEST Structure, IEEE Transactions on Semiconductor Manufacturing, pp. 330-337, Vol. 14, No. 4, 2001), characterize only one aspect of the IC. For example, while the total fabrication cycle might contain up to 450 or more process steps, a CV such as one designed to investigate manufacturability of a single interconnection layer would only need to include a small number, e.g., 10-25 process steps, since active devices and multiple interconnection layers are not required to obtain a yield model or allow accurate diagnosis of the maladies afflicting these steps associated with a single interconnection layer in the process flow.
The use of large numbers of short flow CV's, each on dedicated wafers, is inefficient, problematic, and expensive. Wafers, reticles, and masks for mask sets are quite costly. As will be illustrated later, the presence of large numbers of SF lots in the fabrication facility causes crowding and loading of the fab with engineering lots, particularly at the Front End Of Line (FEOL). It is important to reduce the number of mask layers processed, as well as reducing the number of engineering wafers processed.
A typical single-experiment SF characterization vehicle (wafer) has 5,000-7,500 pads. Accordingly, evaluating all the typical layers in one mask set would require 50,000-75,000 pads. Using current layout and dimensions, a die size of 27 mm×27 mm would be required for the pads only, with no test structures included. This is an unrealistic value.
A typical single-experiment SF wafer requires 5-10 hours for testing. Accordingly, evaluating all the typical layers in one full flow mask set would require 50-100 hours of testing per wafer, corresponding to about three months per lot. This is an unrealistic value, particularly given the necessity for fast feedback loop.
A potential efficiency gain could be achieved by:
a) combining experiments into one mask set; and
b) enabling parallel testing.